A conventional radar sensor unit (radar system) comprises an analog front end (synthesizer, mixer, analog-to-digital converters (ADCs, etc.), a signal processing module/unit (e.g., fast Fourier transforms (FFTs), Digital signal processor (DSP) or a microcontroller unit (MCU). Data processing in the radar system is performed on a system cycle/frame basis.
A frame includes N number of frequency-modulated continuous-wave (FMCW) ramps/chirps. A chirp is a smallest logical unit of data used for radar processing. In classical radar systems, each chirp in a frame includes the same number of ADC samples and the same sampling rate. A typical interface between the ADCs and the signal processing unit is one of the known high speed interfaces (HSIs), such as comprising low-voltage differential signaling (LVDS) or a camera serial interface (CSI, e.g., CSI-2).
One application for radar systems is for automotive collision avoidance. An automotive radar front end needs to transfer the ADC sampled data from received radar signals to the DSP or other signal processing module over the HSI. Each burst of ‘M’ (e.g., 128, 256 or 512) ADC samples that is transmitted over the HSI is called a chirp, and ‘N’ is number of such chirps that make up a radar frame. A DSP typically processes the data frame-by-frame to determine the range, velocity and angle of any obstacle/vehicle in front of the radar system of the vehicle.
In a typical automotive radar system each chirp in the respective frames include the same number of ADC samples. To simplify the design and reduce the cost of additional components such as adding another phase lock loop (PLL)-based clock in the radar system, a pipelined first-in-first-out (FIFO) ping-pong/circular buffer can be used in the receive path. A ping-pong buffer has a divided memory with at least 2 memory blocks (or instances), so that while one memory block is writing received radar information the other memory block can be deleting the previously written information. Such a buffer provides the elasticity and flexibility in choosing the HSI lane data rates decoupled from ADC sampling rate usually specified in several million samples per second (MSPS). With the advancement of CMOS-based radars, it is possible to choose the chirp profiles different within a frame to enhance the radar system performance, typically with the number of ADC samples being different from chirp to chirp in the frames.